1. Field of the Invention
This invention is related to the field of processors and, more particularly, to instruction execution latencies.
2. Description of the Related Art
Processors typically implement instructions which operate on various data types. For example, integer instructions operate on integer data, while floating point instructions operate on floating point data. Generally, floating point data is represented by a sign, a significand (or mantissa), and an exponent. The base for the floating point data may be raised to the exponent power and multiplied by the significand to generate the numerical value represented by the floating point data. Most processors implement the floating point specification promulgated by the Institute for Electrical and Electronic Engineers (IEEE), as specified by IEEE standard 754, etc.
In some cases, the execution hardware implemented by the floating point unit may have a variable execution latency for certain floating point instructions. That is, the execution latency of the instruction is not fixed. This may be problematic if other hardware in the processor is dependent on the execution latency. For example, scheduling hardware may be dependent on the execution latency for selecting when dependent instructions may be scheduled. A mechanism for handling floating point instructions which do not have a fixed execution latency is desired.